Low-power Digital Processing Circuit for Capacitive Accelerometer
A low-power consumption digital processing circuit with large dynamic range and low noise density for micro-machined capacitive accelerometer is proposed.To reduce the power consumption,the sampling rate and the number of logic units used are analyzed.We lower the sampling rate to 2.5MHz which is only one sixteenth of previous scheme.At this frequency,the dynamic range is still as high as 120dB which has been tested.And the dynamic power is as low as 5.4mw which is only about one sixteenth of previous scheme.To reduce the amount of logic units,we adopt square-wave demodulator instead of sinusoidal demodulator (realized by CORDIC algorithm).The entire digital processing circuit with square-wave demodulator uses 577 Slice Registers,about one tenth of the circuit with sinusoidal demodulator.And the dynamic power is even reduced to 0.54mw.Most of all,almost no additional noise is added into this circuit,and the output noise density is as low as 0.01mg/√Hz.
MEMS Accelerometer Low-power consumption Square-wave demodulator
Zhongyi Zhu Yidong Liu Zhonghe Jin
Micro-Satellite Research Center, Zhejiang University, Hangzhou, China
国际会议
中国微米纳米技术学会第14届学术年会、第3届国际年会暨第6届微米纳米技术“创新与产业化国际研讨与展览会(CSMNT2012 & ICMAN2012)
杭州
英文
1-6
2012-11-04（万方平台首次上网日期，不代表论文的发表时间）