65nm layout enhancement and timing closure analysis

摘要：

In this paper, Recommended Design for Manufacture (RDFM) flow is proposed including dummy metal fill, redundant VIAs insertion, layout enhancement, dummy PO/OD insertion to improve chip yield. This flow is targeted at 65nm process. Due to the layout modification imported by RDFM, timing signoff closure is analyzed. Results show that RDFM flow imports about 5％ clock period uncertainty to the design.

关键词： Design for Manufacture 65nm Layout enhancer Timing closure

作者: Gang Zhao Ligang Hou Jiahui Zhu Wuchen Wu Steve Knepper

作者单位: Beijing University of Technology, Chaoyang District, Beijing, China 804 Woburn Street, Boston, Massachusetts, U.S.

会议类型: 国际会议

会议名称: 2012 International Conference on Future Communication and Computer Technology(2012未来通信与计算机技术国际会议ICFCCT 2012)

会议地点: 哈尔滨

会议语种:英文

页码: 37-41

在线出版日期: 2012-05-19（万方平台首次上网日期，不代表论文的发表时间）