An Embedded SRAM IP Compiler Design Methodology Independent of Technology and Circuit Structure

摘要：

this paper presents a novel SRAM IP compiler design methodology that greatly decreases compiler design time and complexity. When designing a new compiler, designers only need to update algorithm written in high level functions and leave rest work to specialized tools which are developed to handle foundry, technology or certain circuit structure relevant information. A new compiler verification approach based on statistics and a Synopsys technology library generating approach based on simulation and interpolation are also discussed in this paper.

关键词： SRAM IP compiler verification timing and power

作者: Cong Wang Ming Liu Hong Chen Xiang Zheng Huamin Cao Zhiqiang Gao

作者单位: Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing 100084, China

会议类型: 国际会议

会议名称: 2012 International Conference on Electric Technology and Civil Engineering(2012 电子技术与土木工程国际会议 ICETCE 2012)

会议地点: 三峡

会议语种:英文

页码: 521-524

在线出版日期: 2012-05-18（万方平台首次上网日期，不代表论文的发表时间）