Design of a multi-functional digital chip in CMOS Process

摘要：

A multi-functional digital chip is designed based on CSMC 2P2M 0.6μm CMOS process. This circuit includes core circuit cell, Level Translator cell, ESD(Electro Static Discharge) protection cell and Output buffer cell.The circuit is simulated using Hspice simulation software and the technology library of the CSMC 2P2M 0.6μm CMOS process(06 mixddct02v24), the layout is based on CSMC 2P2M 0.6μm CMOS, The chip area is 1mm× 1mm. The design has been successfully implemented by participating in the plan of the Multi Project Wafer.Measurements indicate that the wafer achieves the expected goals.

关键词： CMOS Process Multi-functional Digital Chip Layout Design MPW (Multi Project Wafer) Package

作者: Ziang ZHOU Yao YAO

作者单位: Department of Physics and Electronics Engireering Zhoukou Normal University Zhoukou,China

会议类型: 国际会议

会议名称: 2012 International Conference on Electric Technology and Civil Engineering(2012 电子技术与土木工程国际会议 ICETCE 2012)

会议地点: 三峡

会议语种:英文

页码: 647-650

在线出版日期: 2012-05-18（万方平台首次上网日期，不代表论文的发表时间）