A Testable design Method for Memories by Boundary Scan Technique

摘要：

This paper presents a design for test the embedded flash in an object System-on-a-chip (SoC). A is designed to test the embedded Flash. The feature of the Flash TAP (Test Access Port) complies with the IEEE std.1 149.1, and it can select different scan chains and other control registers for other test. By the trade-off between the test time and the circuit area, an IST (In System Test) circuit is designed in the SoC. Experiment results on the embedded memory have shown that the proposed method costs small testing timing by the use of IST.

关键词： Flash Design for test Boundary Scan System on a chip In System Test

作者: Han Ke Deng Zhongliang Gui Qi

作者单位: Beijing Key Laboratory of Work Safety Intelligent Monitoring, School of Electronic Engineering Beiji School of Electronic Engineering Beijing University of Posts and Telecommunications, Beijing, China

会议类型: 国际会议

会议名称: 2012 International Conference on Electric Technology and Civil Engineering(2012 电子技术与土木工程国际会议 ICETCE 2012)

会议地点: 三峡

会议语种:英文

页码: 1342-1345

在线出版日期: 2012-05-18（万方平台首次上网日期，不代表论文的发表时间）