Cache Timing attack against RSA Based on D-Cache
This thesis focuses on the vulnerabilities of the RSA cryptographic algorithm when it is not securely implemented. Simultaneous multithreading enables multiple execution threads to share the execution resources of a superscalar, the shared access to memory caches provides an easily used high bandwidth covert channel between threads, allowing that a malicious thread can monitor the execution of another thread. This paper targets at RSA cryptosystem implemented via OpenSSL0.9.7c, monitors the cryptographic thread by executing a spy thread, recording the timing characteristic during the RSA decryption when reading the Cache. The attacker can recovers the original key via analyzing these timing measurements. Finally, we provide some suggestions of how this attack could be mitigated or eliminated entirely.
RSA Micro-Architectural Analysis Data-Cache Attack Sliding Window Exponentiation Side Channel Attacks
Jingli Qi Fu Sun Jiansi Chen Caisen Chen
Dept. of Training Ordnance Engineering College Shijiazhuang, China Dept. of Computer Engineering Ordnance Engineering College Shijiazhuang, China
国际会议
三峡
英文
1418-1421
2012-05-18（万方平台首次上网日期，不代表论文的发表时间）