A Contrast between Clock Mesh and CTS in ASIC Design

摘要：

In high-performance VLSI chips, the clock distribution architecture can be divided into clock tree and clock mesh by structure. In this paper, clock tree and clock mesh are used to synthesis the same design. Clock skew of the chip with clock mesh structure is 30％ smaller than the chip with clock tree structure. By changing the size of clock mesh, the relationships of total power and total wire length to the mesh size were obtained. The total wire length on chip increases with the clock mesh size. The total power first decreases and then increases as the clock meshs size increases, minimum point of the total power appears.

关键词： Application Specific Integrated Circuit (ASIC) Clock Mesh Clock Tree Synthesis (CTS) Skew Power

作者: Songsong Li Xiaoming Chen Ling Xin

作者单位: School of Information Engineering Dalian Ocean University Dalian, China Faculty of Electronic Information and Electrical Engineering Dalian University of Technology Dalian,

会议类型: 国际会议

会议名称: 2012 International Conference on Electric Technology and Civil Engineering(2012 电子技术与土木工程国际会议 ICETCE 2012)

会议地点: 三峡

会议语种:英文

页码: 2083-2086

在线出版日期: 2012-05-18（万方平台首次上网日期，不代表论文的发表时间）