A High-speed BiCMOS Fully Differential Operational Amplifier With Improved Slew Rate and Phase Margin

摘要：

A high-gain high-speed fully differential foldedcascade operational amplifier with improved slew rate (SR) is implemented in a 0.6-um SiGe BiCMOS process. The amplifier can source/sink much larger current than the quiescent current when output voltage is slewing, even with a current reduction in the common-base path. Compared to the CMOS folded-cascode configuration, BiCMOS folded-cascode improves the phase margin. Cadence Spectre simulation shows that the amplifier has an open-loop DC gain of 103 dB, a unit gain bandwidth of 270 MHz and a phase margin of 63° and a slew rate of 1265 V/μs only consuming 1.6 mA in the main amplifier path, all with 4 pF capacitive loading.

关键词： BiCMOS process fully differential operational amplifier pipeline ADC slew rate component

作者: Feiyan Mu Can Wang Jie Lin

作者单位: Department of Electronic Engineering Chengdu College of UESTC Chengdu, China Long Xin Co. Ltd Chengdu, China

会议类型: 国际会议

会议名称: 2012 International Conference on Computer Science and Electronic Engineering(2012 IEEE计算机科学与电子工程国际会议 ICCSEE 2012)

会议地点: 杭州

会议语种:英文

页码: 652-655

在线出版日期: 2012-03-23（万方平台首次上网日期，不代表论文的发表时间）