Design and Optimization of Ethernet Access System For Receiving Frames of Ethernet Based on FPGA

摘要：

The purpose of this paper is to design and develop an implementation for the underlying data reception on Field Programmable Gate Arrays (FPGA) by top-down structured design. In this paper, we optimize the receiving data function of underlying Ethernet access device, reducing the requirement of the Inter-Packet Gap (IPG) for flow control. It is shown by the test that Ethernet access device dont need IPG for flow control any longer after our optimization.

关键词： IPG Ethernet access Medium Access Control FPGA

作者: Shao En Yuan Dongming Gao Jinchun Liu Yuanan Hu Hefei

作者单位: Beijing University of Posts and Telecommunications Beijing, P.R.China

会议类型: 国际会议

会议名称: 2012 International Conference on Computer Science and Electronic Engineering(2012 IEEE计算机科学与电子工程国际会议 ICCSEE 2012)

会议地点: 杭州

会议语种:英文

页码: 129-133

在线出版日期: 2012-03-23（万方平台首次上网日期，不代表论文的发表时间）