Design and Implementation of H.264/SVC Decoder Forecast Module on ASIC

摘要：

An ASIC front-end design of intra and inter prediction module based on H.264/SVC standard is proposed in this paper. State machine is used in intra prediction module for timing control. A branch reusable unit ADDR3221 is constructed and optimized to implement the intra prediction in RTL-level. In inter prediction module, the three-level MUX is used to realize the level control from the frame-level to block-level. According to the different segmentation of luma and chroma, the computation of the motion vector and interpolation is realized. Simulation and optimization are performed on the EDA tool of Synopsys platform. Experimental results show that the design of the H.264/SVC forecast module fulfills functional integrity, and the power and the area meet the requirement of design constraint.

关键词： Keywords:H.264/SVC intra prediction inter prediction ASIC

作者: CHEN Xi WU Zongze XIE Shengli LIU Jinhai

作者单位: School of Electronic and Information Engineering, South China University of Technology,China,Guangzh School of Electronic and Information Engineering,South China University of Technology, China,Guangzh School of Electronic and Information Engineering, South China University of Technology, China,Guangz

会议类型: 国际会议

会议名称: 4th International Conference on Measuring Technology and Mechatronics Automation(第四届检测技术与机电自动化国际会议 ICMTMA 2012)

会议地点: 三亚

会议语种:英文

页码: 1371-1377

在线出版日期: 2012-01-06（万方平台首次上网日期，不代表论文的发表时间）