A Wrapper of PCI Express with FIFO Interfaces Based on FPGA

摘要：

This paper proposes a PCI Express (PCIE) Wrapper core named PWrapper with FIFO interfaces. Compared with other PCIE solutions,PWrapper has several advantages such as flexibility,isolation of clock domain,etc. PWrapper is implemented and verified on Verlex-5FX70T,which is a development board provided by Xilinx Inc. Architecture of PWrapper and design of two key modules are illustrated,which timing optimization methods have been adopted. Then we explained the advantages and challenges of on-chip interfaces technology based on FIFOs. The verification results show that PWrapper can achieve the speed of 1.8Gbps (Giga bits per second).

关键词： PCI Express FPGA FIFO based interface

作者: Hu Li Yuanan Liu Dongming Yuan Hefei Hu

作者单位: Wireless and EMC Laboratory,Beijing University of Posts and Telecommunications (BUPT),Beijing,China

会议类型: 国际会议

会议名称: 2011 International Conference on Opto-Electronics Engineering and Information Science(2011光电电子工程与信息科学国际会议 ICOEIS 2011)

会议地点: 西安

会议语种:英文

页码: 1074-1077

在线出版日期: 2011-12-23（万方平台首次上网日期，不代表论文的发表时间）