An FPGA-based Intellectual Property Protection Method at Physical Design Level

摘要：

An FPGA-based intellectual property protection method at physical design level is presented for ownership identification in IP reuse. The method uses the special physical structure of FPGA for watermark insertion and adds corresponding checkout mechanism in functional circuit for strengthening robustness. Watermark extractor is designed for extracting watermark by analyzing bitstream. The experimental results on Xilinx Virtex II Pro XC2VP4 shows,the presented method has less resource and timing overhead.

关键词： FPGA IP reuse IP protection

作者: Liang Wei Long Jing Huang Weihong Liu Yuanyuan

作者单位: School of Computer Science and Engineering,Hunan University of Science and Technology,China Department of Electrical Engineering,Guangdong Songshan Polytechnic College,Shaoguang,China

会议类型: 国际会议

会议名称: 2011 International Conference on Opto-Electronics Engineering and Information Science(2011光电电子工程与信息科学国际会议 ICOEIS 2011)

会议地点: 西安

会议语种:英文

页码: 2608-2611

在线出版日期: 2011-12-23（万方平台首次上网日期，不代表论文的发表时间）