Impact of the Parasitic Capacitances with the Change of Distance between Gates of the Split-gate VDMOS

摘要：

A split-gate structure of power VDMOS is proposed in this paper. The p-base of the split-gale VDMOS is formed by self-aligned iun implanted. Only five masks is used to fabrication while the performance of tin- split-gate VDMOS is belter than the conventional VDMOS. Compared to present structure, the split-gale structure can effectively reduce the device parasitic capacitances and the reliability is guaranteed. With the change of the distance between gates of the split-gate VDMOS, impact of the parasitic capacitances is analyzed.

关键词： split-gate VDMOS self-aligned parasitic

作者: Qianwen Chen Quanyuan Feng Senior member

作者单位: Institute of Microelectronics Southwest Jiaotong University Chengdu,China Institute of Microelectronics Southwest Jiaolong University Chengdu,China

会议类型: 国际会议

会议名称: 2011 International Conference on Green Energy and Environmental Sustainable Development(2011年IEEE绿色能源与环境可持续发展国际会议 GEESD2011)

会议地点: 吉林

会议语种:英文

页码: 1246-1249

在线出版日期: 2011-11-04（万方平台首次上网日期，不代表论文的发表时间）