Optimization of QDR SRAM Controller in Network Processor

摘要：

This paper presents a new architecture of shared QDR SRAM controller in the parallel processing of network processor to make the SRAM controller suitable for higher bandwidth and higher speed network communication. With line rate close to dozens of gigabit per second (Gbps), various bottlenecks related with speed, bandwidth and interface must be addressed. The arbitration mechanism is ameliorated so that simultaneous read and write operation to the memory can be executed, and a tag architecture is adopted to keep the special sequence of the SRAM reference. Thus, the bandwidth of the QDR SRAM is highly utilized.

关键词： QDR SRAM high bandwidth arbitration mechanism tag architecture

作者: Kang Li Hongye Jia Honghu Gong Jiangyi Shi Peijun Ma

作者单位: School of Microelectronics, XiDian University Xian, China

会议类型: 国际会议

会议名称: 2011 Fourth International Symposium on Computational Interlligence and Design 第四届计算智能与设计国际会议 ISCID 2011

会议地点: 杭州

会议语种:英文

页码: 254-257

在线出版日期: 2011-10-28（万方平台首次上网日期，不代表论文的发表时间）