Microprocessor Critical Design and Optimization

摘要：

In this paper a 32-bit multithreaded RISC microprocessor is designed and optimized to perform data moving and processing in the high-performance Network Processor which is flexible to a wide variety of networking, communications, and other data-intensive products. As a critical part of network processor, the microprocessor mainly takes in charge of Internet Protocol (IP) packets’ transmitting. Forwarding logic is used to deal with the data hazard, and defer slots are used to deal with the control hazard, besides logic and physical optimizations are employed to solve timing of the critical path.

关键词： microprocessor hazard optimization highperformance

作者: Jiangyi Shi Honghu Gong Hongye Jia Kang Li

作者单位: School of Microelectronics, XiDian University Xi’an, China

会议类型: 国际会议

会议名称: 2011 IEEE 10th International Symposium on Distributed Computing and Applications to Business,Engineering(第十届电子商务、工程及科学领域的分布式计算和应用国际学术研讨会 DCABES 2011)

会议地点: 无锡

会议语种:英文

页码: 347-349

在线出版日期: 2011-10-14（万方平台首次上网日期，不代表论文的发表时间）