Implementation of DES Encryption Algorithm Based on FPGA and Performance Analysis

摘要：

This paper introduced the principle of DES encryption algorithm, designed and realized the DES encryption algorithm with verilog hardware description language, realized module simulation with Quartus II. Two comprehensive considerations from the resources and performance, one pipeline stage control is set in round function to improve the processing speed, Synchronous pipeline architecture of data XOR key round function and Key transformation function is realized on hardware to reducing logic complexity of the adjacent pipeline, round function multiplexing is realized by setting the round counter and controlling the data selector.

关键词： data encryption DES algorithms FPGA Verilog HDL pipeline

作者: Ji HongLian Kai Chen

作者单位: Xian Polytechnic University, Xian, China Kettering University, Flint, United States

会议类型: 国际会议

会议名称: 2011 3nd International Conference on Mechanical and Electronics Engineering(2011年第三届机械与电子工程国际会议 ICMEE2011)

会议地点: 合肥

会议语种:英文

页码: 2953-2956

在线出版日期: 2011-09-23（万方平台首次上网日期，不代表论文的发表时间）