FPGA Based Testing Method to Improve Digital IC Testability

摘要：

With the development of integrated circuit technology, design for test (DFT) is on the agenda. In this paper, we propose a new method that the nontest part of a SIP chip can be easily tested with the boundary-scan test utilizing the boundary scan chain of the FPGA. The problem of no boundary scan test structure in one (or more) chip in a system-inpackage (SIP) can be solved by connecting the interconnection(s) to be tested to the FPGA to form an enlarged boundary scan daisy chain.

关键词： Controllability/Observability boundary scan FPGA

作者: Yinshui Gong Huiyun Li

作者单位: Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences, China The Chinese Universit Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences, China The Chinese Universit

会议类型: 国际会议

会议名称: 2011 3nd International Conference on Mechanical and Electronics Engineering(2011年第三届机械与电子工程国际会议 ICMEE2011)

会议地点: 合肥

会议语种:英文

页码: 3920-3923

在线出版日期: 2011-09-23（万方平台首次上网日期，不代表论文的发表时间）