A Design of VB-DDC using DA-based Systolic FIR Filter
In this paper, we present yet another design of the variable-bandwidth digital down-converter (VB-DDC). The shaping filter in the DDC architecture is substitute with a method which is implemented with fully pipelined computing structure of systolic decomposition for distributed arithmetic (DA) based FIR filer. The systolic structure of the FIR filter involves significantly less memory and complexity compared with the existing ones. The effectiveness of the design is validated by the proposed FPGA implementation results.
digital down-converter distributed arithmetic systolic finite-impulse-response filer
Xu Ping Xia Wei He Zishu
School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu, China
国际会议
合肥
英文
3950-3953
2011-09-23（万方平台首次上网日期，不代表论文的发表时间）