The Dynamic Relocation Cache and Its Energy Consumption Model For Low Power Processor

摘要：

in this paper, a dynamic relocation cache scheme is proposed for low power processor. Based on an energy consumption function of cache system, which mapping the cache energy consumption problem to a binary ILP (Integer Linear Programming) problem, this dynamic relocation cache scheme map the static code to a dynamic location through an address mapping strategy which can relocate the compiler generated code to a single memory with execution sequence, thus provide high performance with small memory capacity. Finally, the full RTL model based on LEON2 processor is implemented and simulated, and the experiment results show that the energy consumption of this cache scheme have approximate 25％ improvement comparing to traditional direct cache scheme for achieving the same IPC (Instructions Per Clock).

关键词： dynamic cache low power ILP formulation

作者: Hongyin Luo Shaojun Wei Donghui Guo

作者单位: Dept. of Electronic Engineering, Xiamen University, Fujian 361005, China Institute of Microelectronics, Tsinghua University, Beijing 100084, China

会议类型: 国际会议

会议名称: 2011 IEEE International Conference on Anti-Counterfeiting Security and Identification(2011防伪、安全及鉴定国际会议 ASID2011)

会议地点: 厦门

会议语种:英文

页码: 123-126

在线出版日期: 2011-06-24（万方平台首次上网日期，不代表论文的发表时间）