CMOS Time-to-Digital Converter with Low PVT Sensitivity 20.8ps Resolution and -0.25~0.22 LSB Inaccuracy

摘要：

A simple but accuracy-enhanced CMOS time-todigital converter (TDC) based on pulse stretcher interpolators is presented. Without the need of modifying the conventional circuit, both inaccuracy and PVT (process, voltage and temperature) sensitivity are substantially reduced. The errors caused by charge injection and clock feedthrough are eliminated by precise device sizing. The accuracy of current and capacitor ratios for its pulse stretchers is ensured by two-dimensional common centroid layouts. Fabricated in a TSMC 0.35m standard CMOS process, the time resolution can be realized as 20.8ps and the INL error is proven to be -0.25~0.22LSB for 0~20ns input range. Moreover, the measured resolution merely spreads over 20.25~20.96ps for twenty packaged chips. All fabricated chips were tested to be full functional under - 40~120℃ temperature operation range and 2.6~4.9V supply voltage range with about ten-fold improvement in temperature drift and supply voltage sensitivity from its predecessor‘s.

关键词： Time-to-digital converter pulse stretcher dual-slop device sizing PVT sensitivity charge injection clock feedthrough

作者: Poki Chen Kai-Ming Wang Chuan-Yuan Li Po-Yu Chen Juan-Shan Lai Cheng-Wei Liu

作者单位: Department of Electronic Engineering, National Taiwan University of Science and TechnologyTaipei, 10 Department of Electronic Engineering, National Taiwan University of Science and Technology Taipei, 1

会议类型: 国际会议

会议名称: 2011 IEEE International Conference on Anti-Counterfeiting Security and Identification(2011防伪、安全及鉴定国际会议 ASID2011)

会议地点: 厦门

会议语种:英文

页码: 127-130

在线出版日期: 2011-06-24（万方平台首次上网日期，不代表论文的发表时间）