A 1.5-bit Pipelined Stage with Time-interleaved Dual-pipeline Architecture used in SHA-less Pipelined ADC

摘要：

A design of a 1.5-bit pipelined stage with timeinterleaved dual-pipeline architecture used in SHA-less pipelined ADC is presented in this paper. Due to the absence of SHA, sampling flash architecture and bootstrapped sampling switch is used to improve the linearity. Op-amp sharing between timeinterleaved dual-pipeline is to reduce power consumption. The sampling network is specially analyzed. The pipelined stage can be used as the first stage of a 10-bit 40 MHz pipelined A/D converter. Simulation by Spectra on 0.18um CMOS process under 1.8V supply voltage shows its SFDR achieves 62 dB near Nyquist input frequency.

关键词： Pipelined ADC SHA-less dual-pipeline boostrapped switch sampling flash architecture

作者: Yan Wang Yuxin Wang Tao Liu Ting Li Jinbao Lan

作者单位: NO.24 Research Institute of CETC NO.24 Research Institute of CETC Science and Technology on Analog Integrated Circuit LaboratoryChong

会议类型: 国际会议

会议名称: 2011 IEEE International Conference on Anti-Counterfeiting Security and Identification(2011防伪、安全及鉴定国际会议 ASID2011)

会议地点: 厦门

会议语种:英文

页码: 131-134

在线出版日期: 2011-06-24（万方平台首次上网日期，不代表论文的发表时间）