A 12-Bit High-Speed ADC Based On GeSi BiCMOS Process

摘要：

In this paper, a 7 stage switched capacitor pipelined ADC is described. This ADC is designed to achieve 12-bit resolution at the speed up to 125MSPS, which uses a fully differential switched capacitor pipelined architecture. This ADC includes an input broadband buffer, which isolates the ADC from external driver circuit, a high performance sample-and-hold amplifier (SHA) front end, and 7 pipelined sub-ADC stages to achieve 12-bit accuracy. A double poly triple metal 0.35μm GeSi BiCMOS process with 5V analog power supply is used in the design. This ADC achieves an SNR of 66dB and an SFDR of 80dB for sampling analog input frequencies up to 50MHz.

关键词： switched capacitor SHA Trimming DEM

作者: Liang Li Xingfa Huang MingYuan Xu

作者单位: National Key Labs of Analog ICs, Chongqing 400060, P.R.China

会议类型: 国际会议

会议名称: 2011 IEEE International Conference on Anti-Counterfeiting Security and Identification(2011防伪、安全及鉴定国际会议 ASID2011)

会议地点: 厦门

会议语种:英文

页码: 146-149

在线出版日期: 2011-06-24（万方平台首次上网日期，不代表论文的发表时间）