A 14bit 10MSps Low Power Pipelined ADC With 0.99pJ/step FOM

摘要：

A 14bit 10MS/s pipelined ADC in 0.18um CMOS process is presented. The amplifier sharing, the SHA removing and scaling down techniques are used for low power. Employing the PCEA (passive capacitor error averaging) technique, the mismatch of the capacitance can effectively overcome. The prototype ADC was fabricated in a 3.3V CMOS process. With a 15.5 MHz input signal, the ADC achieves 82.3dB SFDR and 11.5bit ENOB at 10MS/s. With a 2.4 MHz input signal, the ADC achieves 83.9dB SFDR and 11.75bit ENOB at 10MS/s. The power consumption is 34.2mW at 2.8V supply including output drivers. The chip occupies 2.1*2.1mm2, including pads.

关键词： pipelined ADC amplifier sharing PCEA low power

作者: Ting Li Fule Li Chun Zhang Zhihua Wang

作者单位: Institution of Microelectronics of Tsinghua UniversityBeijing 100084, China Institution of Microelectronics of Tsinghua University Beijing 100084, China

会议类型: 国际会议

会议名称: 2011 IEEE International Conference on Anti-Counterfeiting Security and Identification(2011防伪、安全及鉴定国际会议 ASID2011)

会议地点: 厦门

会议语种:英文

页码: 150-153

在线出版日期: 2011-06-24（万方平台首次上网日期，不代表论文的发表时间）