The 10 GHz Wide Tuning and Low Phase-Noise PLL Chip Design

摘要：

An integer-N phase-locked loop (PLL) operating at 10 GHz is designed and fabricated in TSMC 0.18-um CMOS technology. The proposed PLL with a LC-tank voltage-controlled oscillator (VCO) and a mixed design of current mode logic (CML) and true single phase clock (TSPC) logic in the frequency divider achieves a tuning range from 8.75 GHz to 10.93 GHz and a phase noise of -113.4 dBc per Hertz at an offset frequency of 1 MHz from the carry frequency of 10.49 GHz. The final simulated locking time is lower than 3.7 us. Including pads and an on-chip third-order low-pass filter, the overall chip area is only 0.82×0.68 mm2 (0.56 mm2) as well as the power consumption is 39 mW at the 1.8 V supply voltage.

关键词： PLL phase-locked loop phase noise integer-N multi-modulus frequency divider MMFD

作者: Jhin-Fang Huang Che-Chi Mao Ron-Yi Liu

作者单位: Department of Electronic Engineering, National Taiwan University of Science and Technology Taipei Ta Chung-Hwa Telecom. Lab., Chung-Hwa Telecom. Inc.Taoyuan Taiwan, R.O.C.

会议类型: 国际会议

会议名称: 2011 IEEE International Conference on Anti-Counterfeiting Security and Identification(2011防伪、安全及鉴定国际会议 ASID2011)

会议地点: 厦门

会议语种:英文

页码: 157-160

在线出版日期: 2011-06-24（万方平台首次上网日期，不代表论文的发表时间）