A SHA-less 12-bit 200-MS/s Pipeline ADC
This paper describes a 12-bit, 200MS/s IF sampling pipeline A/D converter (ADC) that is implemented in SMIC 0.13 um CMOS process. The ADC has a sample-and-hold circuit that is integrated in the first pipeline stage, which removes the need for a dedicated sample-and-hold amplifier. In order to decrease the clock jitter effectively, a delay locked loop (DLL) circuit with duty cycle stabilization function is designed. A gain boosting miller compensation two stages OTA is used to achieve the sufficient gain; The use of the redundancy coding technique ease the requirement of the comparator’s offset voltage; On chip reference buffer and High speed LVDS interface are also designed in this ADC. The circuit occupies a chip area of 2mm x 2mm. Simulation result showed that the circuit achieves a SNDR of 73.2 dB and a SFDR of 92 dB at a 1.2V 70MHz sine wave input.
Pipeline A/D converter SHA-less DLL gainboosting Miller compensation OTA On-chip reference Dynamic comparator
Zhao Xiaoxiao Li Fule Bin Wu
Institution of Microelectronics of Tsinghua University,Beijing 100084, China Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
国际会议
厦门
英文
161-164
2011-06-24（万方平台首次上网日期，不代表论文的发表时间）