A CMOS Low Power, Wide Dynamic Range RSSI with Integrated AGC Loop
Abstract- A low voltage low power CMOS limiter and received signal strength indicator (RSSI) with integrated automatic gain control (AGC) loop are designed using TSMC 0.13um CMOS technology. The limiter uses six-stage amplifier architecture for minimum power consideration achieves 56dB gain and 17MHz bandwidth. The RSSI has a dynamic range more than 60dB, and the RSSI linearity error is within ±0.5dB for an input power from -65dBm to -8dBm. The RSSI output voltage is from 0.2V to 1V and the slope of the curve is 14.28mV/dB. The RSSI with integrated AGC loop draws 1.5 mA (I and Q paths) from a 1.2V single supply, including limiters, RSSI and comparators.
LA RSSI AGC comparator
Qianqian Lei Min Lin Miao Peng Zhiming Chen Yin Shi
Department of Applied Electronics, Xi’an University of Technology, Xi’an 710048, P. R. China Suzhou-CAS Semiconductors Integrated Technology Research Center, Suzhou 215021, P.R. China
国际会议
厦门
英文
173-176
2011-06-24（万方平台首次上网日期，不代表论文的发表时间）