Design and Research of Improved Algorithm Decoder of LDPC code

摘要：

Through researching the structural characteristics of LDPC parity matrix and algorithm data flow features of LDPC code, an improved type of algorithm decoder of LDPC code is designed in this paper. The decoder includes expandable storage array, exquisite address-controlling unit and powerful sequential state-controlling machine. It possesses the advantages of expanding the decoding code length flexibly and lower complexity for hardware realizing and higher hardware resource utilization rate. After constructing communication system and testing the performance of hardware decoder, the results showed that the performance of the decoder and the theory simulation value can fit each other perfectly. The correctness of the design is proved. The decoder which is designed in this paper can provide valuable reference for the development of general chips for LDPC decoder.

关键词： communication technology LDPC code serial decoding normalized BPJiased

作者: MENG Qing-gang LIU Teng-yu

作者单位: College of information and communication Engineering Heilongjiang Institute of Technology Harbin, Ch Human Resources Department Heilongjiang Province Higher Peoples Court Harbin, China 150001

会议类型: 国际会议

会议名称: 2012 International Conference on Measurement,Information and Control(2012测量、信息与控制国际会议 ICMIC2012)

会议地点: 哈尔滨

会议语种:英文

页码: 469-473

在线出版日期: 2012-05-18（万方平台首次上网日期，不代表论文的发表时间）