Design of a Low Power Charge Pump Circuit for Phase-locked Loops

摘要：

In this paper, the design of a charge pump circuit suitable for lower power PLL-based frequency synthesizer is presented. The charge pump circuit was designed in 0.18μm CMOS process. The proposed charge pump circuit improves current matching in a wide output voltage range by applying a wide input ranged operational amplifier. The percentage error of current mismatch for the output range from 0.3V to 1.7V is less than ±0.005％. The power consumption of the proposed charge pump circuit is around 0.56mW at a supply voltage of 1.8V.

作者: HuiliXu Zhiqun Li

作者单位: Institute of RF- & OE-ICs, Southeast University Engineering Research Center of RF-ICs & RF-Systems, Institute of RF- & OE-ICs, Southeast University Engineering Research Center of RF-ICs & RF-Systems,

会议类型: 国际会议

会议名称: 2012 4th International High Speed Intelligent Communication Forum(2012年国际高速智能通信论坛 HSIC2012)

会议地点: 南京

会议语种:英文

页码: 88-91

在线出版日期: 2012-05-17（万方平台首次上网日期，不代表论文的发表时间）