Design of a Low-Voltage High-Speed CMOS Integer-M Frequency Divider in WSN Applications
A SGHz low-voltage CMOS integer-M frequency divider whose modulus can be varied from 2403 to 2480 for WSN applications is presented in this paper. The divider contains two blocks, a dual-modulus prescaler (DMP), which adopts the structure of the pseudo-differential static D-type flip-flop, and a pulse-swallow counter. The whole frequency divider is designed in 0.18um CMOS process and the simulation results illustrate that the divider can operate normally over a wide range of 4-6 GHz which consumes 1.89mA at 1V.
Yu Lu Fan Xiangning
Institute of RF- & OE-ICs, School of Information Science and Engineering Southeast University, Nanjing 210096, China
国际会议
2012 4th International High Speed Intelligent Communication Forum(2012年国际高速智能通信论坛 HSIC2012)
南京
英文
106-109
2012-05-17（万方平台首次上网日期，不代表论文的发表时间）