An Adaptive Modular Reduction Based Error- Detection Algorithm

摘要：

In this paper, an adaptive modular reduction based error-detection algorithm is proposed, it is based on the research of the modular reduction model and the missing rate of residue code. In the proposed method, more than one moduli are used to detect the input before they being sent into the functional logic, then the best modulus is chosen accordingly to optimizing the error detection performance. The simulation shows that, for the frequently-used unit in signal processing, such as addition and multiplication, fault missing rate of the proposed method is lower than that of the regular method under the same circuit size. And the cost of the detection branch in the proposed method is lower than that in the regular method under the same fault missing rate.

关键词： SEU FPGA modular reduction

作者: Zuobiao Yin Wenhui Yang Jianping Xiong

作者单位: Department of Precision Instruments and Mechanology, Tsinghua University, Beijing, 100084, P.R. Chin Department of Communication Engineering, Xiamen University, Xiamen, 361005 J.R.China

会议类型: 国际会议

会议名称: 2012 4th International High Speed Intelligent Communication Forum(2012年国际高速智能通信论坛 HSIC2012)

会议地点: 南京

会议语种:英文

页码: 197-200

在线出版日期: 2012-05-17（万方平台首次上网日期，不代表论文的发表时间）