A 20GS/s Low-Power BiCMOS Comparator Using an Active Inductor Load
A 20GS/s BiCMOS hitched comparator for highspeed, low-power Analog-to-Digital Converter (ADC) is proposed. The resister load of conventional currentsteering comparator is replaced by an active inductor load made by a MOS transistor and a resister. This solution extends the bandwidth of the circuit without excessive power dissipation. Implemented in 0.35μm SiGe BiCMOS technology, this comparator only occupies a die area of 97×67 μm2 with a power dissipation of 31 mW from a 3.3-V power supply. Operating with an input frequency of 2 GHz, the circuit can oversample up to 20 GS/s with 4 bits of resolution; while operating at Nyquist, the comparator can sample up to 20 GS/s with 3 bits resolution. This design achieves a considerable tradeoff between power, speed and resolution.
Kuai Yin Qiao Meng Kai Tang Yi Zhang
Institute of RF- & OE-ICs, Southeast University, Nanjing, China
国际会议
2012 4th International High Speed Intelligent Communication Forum(2012年国际高速智能通信论坛 HSIC2012)
南京
英文
261-264
2012-05-17（万方平台首次上网日期，不代表论文的发表时间）