Design and Implementation of a New Pipelined H.264 Encoder
In order to get better coding effect, H.264 adopts an algorithm with high computation complexity, which makes the architecture directly influence the performance of encoder. It is important to design an efficient architecture for H.264 encoder. This paper presents a new five-stage pipelined architecture of H.264 encoder. Existing H.264 encoders adopt fourstage pipelined architecture, whose critical path is too long due to the high computation complexity of integer motion estimation (IME) stage. In this paper, we separate off-chip data read from IME and make it a substantive stage, which shortens the critical path and improves the performance of encoder. Besides, an optimized motion estimation (ME) algorithm is adopted to remove data dependencies and shared storage policies are adopted to save hardware resources. The H.264 baseline profile is successfully mapped into hardware with the proposed architecture, which can encode 720p 30 fps videos in real time at 93 MHz.
H.264 encoder five-stage 720p system structure
Bin Qi Duoli Zhang Yukun Song Gaoming Du Yong Zheng
Institute of VLSI Design Hefei University of Technology Hefei, China
国际会议
哈尔滨
英文
130-133
2011-12-24（万方平台首次上网日期，不代表论文的发表时间）