Design of Intra Prediction Module in H.264 and AVS Dual Modes Video Decoder Chip

摘要：

This paper introduces the structure of intra prediction module, which has been implemented with Verilog hardware language, in H.264 and AVS dual modes video decoder chip. Firstly, the video coding standards and their principle are introduced. Then a highly efficient hardware architecture is given based on the analysis of intra prediction algorithm in H.264 and AVS. This design reuses some modules according to the common of H.264 and AVS in architecture and algorithm, in particular the PE processing unit. The parallel pipeline and memory controller are also adopted to enhance the decoding efficiency. Finally, the design passes the FPGA verification, which its results of simulation and synthesis show that the timing and area requirements of chip design are both satisfied.

关键词： H.264 AVS video decoder chip intra prediction FPGA

作者: Shouheng Xu Yuelin Xing Xianzheng Wei

作者单位: School of Information Science and Engineering Shandong University Jinan, China

会议类型: 国际会议

会议名称: 2011 International Conference on Computer Science and Network Technology(2011计算机科学与网络技术国际会议 ICCSNT 2011)

会议地点: 哈尔滨

会议语种:英文

页码: 635-638

在线出版日期: 2011-12-24（万方平台首次上网日期，不代表论文的发表时间）