A 5-Stage Pipelined Embedded Processor with Optimized Handling Exception
This paper presents the design and implementation of a embedded processor, xCoreAHB, featuring precise interrupt and exception, which is compatible with ARMv4 architecture. The precise exception mechanism of this design provides not only the quick entrance of the interrupt handle programs but also the interrupt handle programs with the right return address by an additional program counter in write back stage of the pipeline and its support circuits. The proposed exception controller saves about 30％ area compared with the traditional exception controller. The proposed design has been implemented with the 0.18um 1P6M CMOS process of SMIC. The chip operates 1.2DMIPS at a frequency of 100MHz with 33mW power dissipation.
precise exception embedded processor RISC ARM
Wenjiang Li Song Zhang Xiong Jiang Yaohui Zhang
Division of System Integration & IC Design Suzhou Institute of Nano-Tech and Nano-Bionics, CAS Suzho Division of System Integration & IC Design Suzhou Institute of Nano-Tech and Nano-Bionics, CAS Suzho
国际会议
哈尔滨
英文
2773-2777
2011-12-24（万方平台首次上网日期，不代表论文的发表时间）