HIGH SPEED DATA PROCESSING SOPC SYSTEM BASED ON NIOS Ⅱ RECONFIGURABLE SOFT IP CORES
A high speed data processing system has been designed based on NIOS Ⅱ reconfigurable soft IP cores.The mainly task of the system is to process data at high speed meanwhile to ensure the correctness of data.In this condition, user-defined SRAM logic controller combine complex flash operate mode has been designed to deal with plenty of data at high speed take the advantage of the reconfigurable characteristic of soft IP cores.System signal bit is 16, update speed is 10MHz and signal enable period is 15.3ms.SRAM using pingpang change structure processing data.By generating SRAM hardware interrupt changing Avalon bus control right and adding user-defined information such as head, time stamp ,data length and so on to ensure the correctness of data.System resource usage condition and power consumption also mentioned in detail.Wideband input voltage designed adapted to remote system control requirement.Through long time use, system has high reliability and stability.
SOPC (System-on-a-programmable chip) Nios Ⅱ processor FPGA,Soft IP cores data processing
HUANG XIAOYAN GAO TIANDE FENG XIAN
College of marine Northwestern Polytechnical University,NWPU Xian ,China
国际会议
成都
英文
461-465
2011-11-25（万方平台首次上网日期，不代表论文的发表时间）