OPTIMIZATION OF HALF-PIXEL INTERPOLATION FOR H.264/AVC BASED ON C64X+ DSP1

摘要：

This paper proposed a novel half-pixel interpolation implementation scheme of H.264/AVC based on the resource of C64x+ DSP (Digital signal processor) and characteristic of cache on TMS320C64x+ platform. Firstly, the theory of H.264 half-pixel interpolation was analyzed.Then half-pixel horizontal interpolation process was optimized with a parallel computing pattern.For further reducing the cache miss rate and cache bank conflicts, Half-pixel vertical interpolation process was equally transformed to matrix transposition and horizontal interpolation process.Finally, the optimized scheme were realized by linear assembly language, Simulation results show that the optimized scheme was effective and could result in 3.5 times speed accelerating.In addition, there was no performance loss during the optimized scheme process.

关键词： Half-pixel interpolation linear assembly H.264/AVC cache TMS320C64x+

作者: Haibo Wang Deming Cheng Zhe Li

作者单位: Beijing Key Laboratory of Digital Media,School of Computer Science and Engineering,Beihang University,Beijing 100191,China

会议类型: 国际会议

会议名称: 2011 3rd International Conference on Computer Technology and Development(2011第三届计算机技术与发展国际会议 ICCTD2011)

会议地点: 成都

会议语种:英文

页码: 1206-1211

在线出版日期: 2011-11-25（万方平台首次上网日期，不代表论文的发表时间）