Design and Implementation of an FPGA-Based High-Performance Improved Vector-Reduction Method

摘要：

Vector-reduction operation is the basis of many scientific computations. FPGA-based vector-reduction circuit must use deeply pipelined floating-point IP cores to gain a performance advantage over generalpurpose processor (GPP). Improper design of reduction circuit will destroy the benefit from pipelining or impose unrealistic buffer requirements. In this paper, a high-performance improved reduction method is proposed and analyzed for FPGA platform. This design runs in optimal time while requires only four buffers of fixed size and a single pipelined floating-point unit. Using ALTERA Cyclone II EP2C70F896C6 as the target device, we implement vector summation which is most common example of vector-reduction using improved reduction method.

关键词： Computer Arithmetic FPGA Pipelined Floatingpoint IP Cores Vector-Reduction

作者: Qingzeng Song Junhua Gu Jinzhu Zhang

作者单位: College of Electrical Engineering and Automation, Hebei University of Technology, Tianjin, China College of Computer Science and Software, Hebei University of Technology. Tianjin, China College of Architecture and Art Design Hebei, University of Technology, Tianjin, China

会议类型: 国际会议

会议名称: 2011 International Conference on Electronics and Optoelectronics(2011电子学与光电子学国际会议 ICEOE 2011)

会议地点: 大连

会议语种:英文

页码: 52-55

在线出版日期: 2011-07-29（万方平台首次上网日期，不代表论文的发表时间）