Asynchronous FIFO Implementation Using FPGA

摘要：

We introduce a design of asynchronous FIFO on FPGA for the purpose of high-speed, steady data transmission between asynchronous clock domains. In the design , the memory address was organized into one ring list, using gray code as its address code, making uses of double jump technology to finish two asynchronous clock regions between address signals transmission, avoiding the meta-stability well.

关键词： FPGA asynchronous FIFO grey code doublejump technology

作者: Yanjun Zhang Chunli Yi Jinqi Wang Jinye Zhang

作者单位: Key Laboratory of Instrumentation Science & Dynamic Measurement(North University of China Ministry o Key Laboratory of Instrumentation Science & Dynamic Measurement(North University of China Jin xi industrial group technology center Taiyuan, Shanxi Province, China

会议类型: 国际会议

会议名称: 2011 International Conference on Electronics and Optoelectronics(2011电子学与光电子学国际会议 ICEOE 2011)

会议地点: 大连

会议语种:英文

页码: 666-668

在线出版日期: 2011-07-29（万方平台首次上网日期，不代表论文的发表时间）