The Design of a 5 GHz Programmable Frequency Divider for Fractional-N Frequency Synthesizer

摘要：

The design of a high speed programmable frequency divider for fractional-N frequency synthesizer is presented.The programmable divider consists of a divide-by-4/5 dual-modulus prescaler, a 5-bit programmable counter, and a 2-bit swallow counter.A new scheme of reload operation is adopted to reduce the propagation delay of the critical path.The triggering signal for the two counters is selected carefully to mitigate the timing requirement of the mode control signal.The divider is designed in 0.18 um CMOS process.Its division ratio (DR) covers the range from 12 to 127.Post-layout simulations show it can work up to 5 GHz under 1.8 V power supply, while consuming only 9 mW and occupying an area of about 0.06 mm2.

关键词： Programmable frequency divider reload operation mode control

作者: Zhongshan Chen Yan Tu Liang Feng

作者单位: Southeast University,Nanjing,China Yancheng Institute of Technology,Yancheng,China Southeast University,Nanjing,China Yancheng Institute of Technology,Yancheng,China

会议类型: 国际会议

会议名称: 2011 2nd International Conference on Material and Manufacturing Technology(2011第二届材料与制造技术国际会议 ICMMT2011)

会议地点: 厦门

会议语种:英文

页码: 623-628

在线出版日期: 2011-07-08（万方平台首次上网日期，不代表论文的发表时间）