Statistical Time Division Multiplexing Based Local System Architecture for Multi- Cluster NoC
In order to eliminate the inefficiency of the conventional bus based architecture, network-on-chip (NoC) has been suggested as a novel approach for several years. Considering the trend that hundreds or even thousands of IP blocks will be integrated on a chip, the concept of multi-cluster NoC is proposed. It usually adopts the hybrid architecture mixed with bus based local system and mesh based global topologies. However, the nature difference between these two topologies brings in extra communication costs which will finally influence the overall performance. In this paper, a statistical time division multiplexing (STDM) based architecture for local system is proposed with the goal of reducing the costs so as to optimize the whole system performance. Furthermore, novel packet formats are designed by using the feature of STDM aiming at maximizing the utilization of packets. And the mechanism of waiting is introduced in the network interface (NI) module to improve the performance further. A cycle accurate systemC platform is built and experimental results verify that the proposed architecture can save network loads and reduce the transmission delay sharply. In the best condition, the improvement can reach 55％ and 63-3％ respectively compared with the contrast.
Network-on-chip Multi-Cluster NoC Statistical Time Division Multiplexing Cluster Architecture
Wang Jiawen Li Li Zhang Yuang Pan Hongbing He Shuzhuan Zhang Rong
Institute of VLSI Design, Nanjing University LAPEM, Nanjing University Nanjing, Jiangsu 210093, China
国际会议
西安
英文
472-476
2011-05-27（万方平台首次上网日期，不代表论文的发表时间）