Design and Implementation of Area-optimized AES Based on FPGA

摘要：

A new FPGAbased implementation scheme of the AES128 (Advanced Encryption Standard, with 128bit key) encryption algorithm is proposed in this paper. For maintaining the speed of encryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that the chip size can be reduced. The 128bit plaintext and the 128 bit initial key, as well as the 128bit output of ciphertext, are all divided into four 32bit consecutive units respectively controlled by the clock. The synthesis verification based on HJTC0.18um CMOS process shows that this new program can significantly decrease quantity of chip pins and effectively optimize the area of chip.

关键词： Areaoptimization Pipelining Verilog FPGA

作者: AI-WEN LUO QING-MING YI MIN SHI

作者单位: College of Information Science and Technology Jinan University Guangzhou, China College of Information Science and TechnologyJinan UniversityGuangzhou, China

会议类型: 国际会议

会议名称: 2011 International Conference on Business Management and Electronic Information(2011商业管理与电子信息国际学术会议 BMEI2011)

会议地点: 广州

会议语种:英文

页码: 1-4

在线出版日期: 2011-05-13（万方平台首次上网日期，不代表论文的发表时间）