Verification Platform Research Base on SystemC Design
With the development of electronics, the design of hardware becomes more and more complicated, which increase the difficulty of validation accordingly. Hardware and software design cooperatively on simulation and verification, which not only solve the problems of Hardware Model on higher levels, but it also has become a popular design method. The effectiveness of programming languages on systemlevel and servicelevel is remarkable. As a result, the paper introduces the practicability of SystemC on Hardware Model, and makes great play with the function and method of verification. At last, full adder Hardware Model is established successfully.
SystemC SCV verification fulladder SoC
Fan LIAO Shilei SHAO Shuhua TENG
Postgraduate Team 4 ICE , Communication Engineering Institute, PLA University of Science and Technol Department of Telecommunication Engineering ICE, PLA University of Science and Technology,NanJing, 2 College of Electronic Science & Engineering, National University of Defense Technology, Changsha, 41
国际会议
广州
英文
1-4
2011-05-13（万方平台首次上网日期，不代表论文的发表时间）