A 1mW multi-channel 12-bit SAR A/D Converter

摘要：

Design and realization of an 8-channel 12bit SAR A/D converter (ADC) is described in this paper. Based on the successive approximation register (SAR) architecture, this A/D Converter has a maximum sample rate of 140KSPS and the entire ADC consumes only 1mW from a 1.8V supply and the shutdown current is only 1uA. The low-power ADC was fabricated by a 0.18μm 2P4M CMOS process. The layout area of the ADC is 0.3 mm 0.35 mm. At the high performance point (12-bit, 140KSPS), the INL and DNL of the ADC are 0.7LSB and 0.66LSB, respectively.

关键词： SAR ADC DAC CMOS Multi-channel

作者: Liu Hongbing Chen Weibing Tan Chuanwu

作者单位: Dept. of Electrical Engineering, Hunan Railway Professional Technology College, Zhuzhou 412001, Chin School of Computer and Communication, Hunan University of Technology, Zhuzhou, Hunan, 412008, China

会议类型: 国际会议

会议名称: 2012 International Conference on Intelligent System Design and Engineering Applications(2012年智能系统设计与工程应用国际会议 ISDEA 2012)

会议地点: 三亚

会议语种:英文

页码: 1173-1175

在线出版日期: 2012-01-06（万方平台首次上网日期，不代表论文的发表时间）