ATPG of Digital Electronic Systems BIST Based on D-PL Chaotic Model

摘要：

A D-PL ( Digital -PL) chaotic model was proposed to construct ATPG (Automatic Test Pattern Generation) of BIST (Built in Self Test) in this paper. The D-PL chaotic model is improvement of the traditional continuous PL chaotic model. The coefficient of power of 2 was used for traditional PL chaos discrete processing. This approach is conducive to the realization of hardware. Shift registers and accumulator adopted to implement iteration avoiding the direct use of the multiplier. This method can effectively reduce the circuits area After parameters optimization, the D-PL chaotic model ATPG was applied for testing digital circuits. Experiment results show that the proposed D-PL chaotic model ATPG has good randomness and ergodicity. The test pattern of D-PL Model has no correlation. It can effectively improve the digital circuits fault detection rate in BIST.

关键词： digital-PL chaos binary time series correlation auto test pattern generation (ATPG).

作者: Min Zhu Yu Chen Chunling Yang Dongyang Zhao

作者单位: School of Electrical Engineering and Automation, Harbin Institute of Technology, Harbin 150001, P.R. Beijing Institute of Computer Application, Beijing, 100089, P.R.China

会议类型: 国际会议

会议名称: 2012 International Conference on Intelligent System Design and Engineering Applications(2012年智能系统设计与工程应用国际会议 ISDEA 2012)

会议地点: 三亚

会议语种:英文

页码: 1200-1203

在线出版日期: 2012-01-06（万方平台首次上网日期，不代表论文的发表时间）