Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application

摘要：

CORDIC plural-multiplier is the key module to affecting the speed and accuracy of FFT processor. Considering these demands, the problem of CORDIC algorithm is discussed in detail and the according optimization methods are given in this paper. Then, the hardware pipelining structure of the CORDIC multiplier is put forward. Comparison results about RTL simulation results with MATLAB calculation indicate that the design is feasible and practical.

关键词： CORDIC algorithm FFT Pipeline structure Plural-Multiplier

作者: Shi Jiangyi Wang Mingxing Tian Yinghui Yang Zhe

作者单位: Dept Microelectronics, Xidian University, Xian, Shaanxi, 710071, China

会议类型: 国际会议

会议名称: 2012 International Conference on Intelligent System Design and Engineering Applications(2012年智能系统设计与工程应用国际会议 ISDEA 2012)

会议地点: 三亚

会议语种:英文

页码: 1220-1223

在线出版日期: 2012-01-06（万方平台首次上网日期，不代表论文的发表时间）