The design of high performance Barrel Integer Adder

摘要：

This paper proposes a new kind of parallel integer addition algorithm - the barrel integer addition algorithm on the basis of researching the structure of half adder. It also elaborates the principle and structure of barrel integer addition algorithm, analyses the time and the degree of complexity in the area of the algorithm and at the same time compares it with the traditional integer addition algorithm. We realized that the 16-bit barrel integer adder using Verilog HDL and verifies comprehensively in the Altera device. The result shows that the speed of the barrel integer adder designed in this paper improves obviously on the basis of a small increase of area, which lays the foundation for the improvement of the multiplier performance.

关键词： half adder barrel integer adder FPGA algorithm

作者: ZhangZhen FengJing ZhangHaitao

作者单位: Enrollment Employment Department of ChangSha University Mechanization Design Department of BERIS Engineering and Research Corporation School of Electronic and Communication, Changsha University

会议类型: 国际会议

会议名称: 2012 International Conference on Intelligent System Design and Engineering Applications(2012年智能系统设计与工程应用国际会议 ISDEA 2012)

会议地点: 三亚

会议语种:英文

页码: 1310-1314

在线出版日期: 2012-01-06（万方平台首次上网日期，不代表论文的发表时间）