Failure Analysis on Open defect with Logic Time Sequence Analysis and Simulation Experiment Method
FA (Failure Analysis) plays an important role in VLSI designing and manufacturing. In FA we usually handle the cases with open failure which we can’t use FA tools (OBIRCH, EMMI and so on) to capture its location effectively. Therefore, it is an obstacle to improve success ratio of FA and reduce microprobing workload. In this paper, we proposed one FA idea to analyze gate floating when there were abnormal output, normal input and normal IV curves. And one LTS (logic time sequence) analysis and simulation experiment methods for open failure were introduced. Then, three real cases were shared with open contact, open via and open metal line defects respectively. The idea and method could not only provide novel and simple FA method for open failure, but also reduce microprobing workload and improve success ratio for FA case.
Open Failure Logic Time Sequence Analysis Simulation Experiment Failure Analysis
Li Tian Miao Wu Chunlei Wu Diwei Fan Gaojie Wen Winter Wang
Product Analysis Laboratory of Quality Department in Freescale Semiconductor(China) Limited, Tianjin, China
国际会议
三亚
英文
1422-1425
2012-01-06（万方平台首次上网日期，不代表论文的发表时间）