FPGA Based High Speed Design for Blind Equalization of 8PSK Signals

摘要：

A high speed structure for blind equalization of 8PSK signals is presented based on FPGA. The filter section is designed with a parallel structure based on time-domain convolution. In the case of short delay spread, this structure is superior to the parallel structure based on sub-convolution filter bank in literature on computational complexity. Applying this structure to the blind equalization of 800Mbps 8PSK signals, test results show that the speed requirement is met, the hardware resources are furthest saved, and the blind equalizer converges fast.

关键词： adaptive filtering constant modulus algorithm subconvolution filter bank blind equalization

作者: Jiang Bo Li Quanna Xu Tao Liu Cuihai Wen Dong

作者单位: department of navigation and communication, navy submarine academy, Qingdao, China

会议类型: 国际会议

会议名称: 2011 the Iet 4th International Conference on Wireless,Mobile & Multimedia Networks(第四届无线、移动及多媒体网络国际会议 ICWMMN2011)

会议地点: 北京

会议语种:英文

页码: 192-195

在线出版日期: 2011-11-27（万方平台首次上网日期，不代表论文的发表时间）