A systolic bit-parallel multiplier with flexible latency and complexity over GF(2m) using polynomial basis

摘要：

This paper presents a systolic bit-parallel multiplier with flexible latency and complexity over GF(2m) using polynomial basis. Via the employment of shift register array and pipeline strategy, the multiplier designed in this paper is able to work pipelining parallel with smaller critical path. A cell which could reach the function of reducing the input operand’s degree by one and add the results of different degrees together is created in this paper. The systolic bit-parallel multiplier can be made of several such cells. Several multipliers which have different latencies and complexities with pipeline strategy are created with further discuss, the comprehensive performances of these designs are estimated with the parameter of area-time. At the end of the page, we compare the systolic bit-parallel multiplier of this paper with a certain number of typical designs these years, the result shows that the design in this paper obtains a comprehensive performance improvement by 70％, 27％ and 31％.

关键词： systolic bit-parallel multiplier flexible latency and complexity polynomial basis pipeline

作者: Jingxian Zhang Zheng Song Qingsheng Hu

作者单位: Electronic Engineering, Nanjing University of Posts &Telecommunications, Nanjing 210046, China Electronic Engineering, Nanjing University of Posts &Telecommunications, Nanjing 210046, Chinaa

会议类型: 国际会议

会议名称: 2011 International Conference on Advanced Materials and Engineering Materials(2011先进材料与工程材料国际会议 ICAMEM 2011)

会议地点: 沈阳

会议语种:英文

页码: 848-855

在线出版日期: 2011-11-22（万方平台首次上网日期，不代表论文的发表时间）