Digitally assisted backend correction pipeline ADC Verilog-A modeling

摘要：

In this paper, a 12 bits pipeline ADC (analog to digital converter) based on digitally assisted backend correction is described and behaviorally modeled in Verilog-A language. The Verilog-A model is simulated with Cadence Spectre simulator. In the traditional use of pipeline ADC, the for-end sample and hold amplifier occupies the most power consumption. To decreases the system power consumption, open-loop amplifier is used in the first residual amplify circuit between first and second stage sub-ADC. To correct the nonlinear error introduced by the open-loop amplifier, backend digitally correction is applied.

关键词： Backend correction Digitally assisted Pipeline ADC Open-loop amplifier Verilog-A

作者: GONG Yuehong LUO Min MA Jianguo

作者单位: Micro electronics and solid-state electronics department, Harbin Institute of Technology, harbin,Hei Microelectronic R&D center, Harbin Institute of Technology in Weihai, Weihai, Shangdong 264209, Chin

会议类型: 国际会议

会议名称: 2011 International Conference on Advanced Materials and Engineering Materials(2011先进材料与工程材料国际会议 ICAMEM 2011)

会议地点: 沈阳

会议语种:英文

页码: 1122-1128

在线出版日期: 2011-11-22（万方平台首次上网日期，不代表论文的发表时间）